IEEE

Performance Enhancement of GaN Super-Lattice Castellated Field-Effect Transistors (SLCFETs) via Topside Integration of Near-Isotropic Polycrystalline Diamond

Abstract: We present the performance enhancement of GaN super-lattice castellated field-effect transistors (SLCFETs) following the integration of near-isotropic polycrystalline diamond (PCD) on top as ...
IEEE

Reducing Transistor Count in CMOS Logic Design Through Clustering and Library-Independent Multiple-Output Logic Synthesis

Abstract: We propose a novel transistor-level synthesis method to minimize the number of transistors needed to implement a digital circuit. In contrast with traditional standard cell design methods or ...