In previous articles, we gave an overview about secure SoC architectures (Part I) , about the importance of key management (Part II) and secure boot (Part III) - the first line of defense. Part IV of ...

Bus developed by the MIPI Alliance is a two-wire interface built on the foundation of I2C with advancements to improve speed and efficiency. It is designed to replace I2C (and partially SPI) while ...

Mirabilis Design Inc. provides system-level modeling solutions that reduce the risk and time-to-market of complex electronic systems. VisualSim, the company’s flagship product, is used by hundreds of ...

Use of these SerDes interfaces is essential because they enable: High-speed, low-latency data transfer: A SerDes interface allows for the efficient transmission of large amounts of data at high speeds ...

June 23, 2025 -- BOS Semiconductors is proud to announce our membership in VESA (Video Electronics Standards Association) and UCIe (Universal Chiplet Interconnect Express) —two global alliances ...

Siemens is demonstrating a new EDA AI system specifically designed for semiconductor and PCB design environments. The purpose-built EDA AI system delivers secure, advanced generative and agentic AI ...

QuickLogic Corporation (NASDAQ: QUIK), a developer of embedded FPGA (eFPGA) Hard IP, ruggedized FPGAs, and FPGA User Tools, today announced that it joined the newly launched Intel Foundry Chiplet ...

As chip design becomes increasingly complex with more components, higher performance demands and tighter timelines, Magillem Packaging helps engineering teams work faster and more efficiently by ...

Rapidus Corporation, a manufacturer of advanced logic semiconductors, today announced a strategic collaboration with Siemens Digital Industries Software for semiconductor design and manufacturing ...

T2M-IP, the global independent semiconductor IP Cores provider and technology expert, proudly announces the availability of its certified, qualified, and widely deployed Automotive Interface IP Cores, ...

The innovative digital control algorithm used in the Ultra+ PLL achieves unprecedented loop bandwidth precision, enabling user-defined settings as accurate as 0.1% of Fref – with further accuracy ...

Predrag Nikolic, Technical Lead at Veriest will host a special session "AI-Enabled EDA for Chip Design" on Tuesday, June 24, from 10:30 AM-12:00 PM, featuring seven founders pioneering AI-driven ...