EDN

Verifying large models in RTL simulation

Verifying that a multi-million gate ASIC will function according to its specification prior to being built into a system composed of hundreds or thousands of additional ASICs plus thousands of other ...
Design-Reuse

Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs

The latest release of HES-DVM™ provides a simulation acceleration flow, providing significant RTL simulation speed-up of designs targeting Microchip FPGA devices. Henderson, NV, USA – November 3, 2020 ...
EDN

Modeler connects RTL, SystemC simulation

SAN JOSE, Calif. — Adding a proverbial tiara to its Miss Univers line of hardware/software co-verification tools, Adveda Inc. is introducing this week a model generator simulation add-on that places a ...
Semiconductor Engineering

Distributing RTL Simulation Across Thousands Of Cores On 4 IPU Sockets (EPFL)

“Hardware development relies on simulations, particularly cycle-accurate RTL (Register Transfer Level) simulations, which consume significant time. As single-processor performance grows only slowly, ...
Electronic Design

How to Become an RTL Simulation Expert vs. Hardware Emulation Expert

In Part 1, we reviewed the process of designing a modern hardware emulation platform. Here, we’ll look at the skills and training that are necessary to become a simulation expert and an emulation ...
Business Wire

Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has introduced a HES-DVM™ simulation ...
Design-Reuse

Verifying large models in RTL simulation

Verifying that a multi-million gate ASIC will function according to its specification prior to being built into a system composed of hundreds or thousands of additional ASICs plus thousands of other ...