EDN

Re-Energizing Input Buffer Schemes: Part 1

A fundamental component of high-speed optical networking equipment designs are a low-cost, high-bandwidth interface for the network processors. Traditionally, designers have implemented these ...
Design-Reuse

Realizing the Performance Potential of a PCI-Express IP

Interconnect standards such as PCI Express, Hyper Transport and Rapid IO have several common features such as packet based transmission, flow control for buffer space management, data integrity checks ...
EDN

JESD204B Subclasses (part 1): Intro and Deterministic Latency

Unquestionably, a hallmark of the Information Age is an explosion in the need to collect, process, and distribute larger and larger chunks of data. In communications networks, this means more ...
Semiconductor Engineering

Jitter Budgeting For Clock Distribution Networks In High-Speed PHYs And SerDes

This paper presents a simple but practically precise estimation of periodic single-tone power supply induced jitter (PSIJ) for MOS clock buffer chains. The estimation is algebraically simple for its ...
Streaming Media Magazine

Encoding Best Practices to Reduce Latency

Watch the complete panel from Streaming Media East Connect, Latency Still Sucks (and What You Can Do About It) on the Streaming Media YouTube channel. Learn more about low-latency streaming at ...
Streaming Media Magazine

Glass-to-Glass Report: Comparing Low-Latency Streaming Providers

In this article, I examine low-latency services provided by streaming CDNs, removing actual vendor names and making conclusions based on delivery method. I’ll start with a discussion of the basics of ...
TweakTown

Intel is working on the holy grail of frame generation: AI-generated and no input latency

TL;DR: Intel's research paper introduces G-buffer Free Frame Extrapolation (GFFE) for low-latency real-time rendering, aiming to improve frame generation without added latency. Unlike traditional ...